TVHSAC 2013 - Call for Participation

CALL FOR PARTICIPATION

Scope -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope

Demand for higher bandwidths never lets up in the world of communication and networks. While we struggle today to make 40Gbps line-rates a reality, plans are already afoot for 400Gbps. Similarly in wireless communications, 60Ghz is coming on-line today, but designers are already planning the next few generations up to Thz. What is high-speed? It clearly depends: on the medium of transmission, on power constraints, on process technology, on link parallelism, on cost and quality requirements and on the electrical and thermal environment of operation. These constraints define a multi-dimensional box that designers are placed in and asked to provide the highest bandwidth they can, inside a room whose walls seem constantly to move inwards. A lot of the functionality is increasingly analog with strict standards regulating their design and use. And it is a race with no end in sight.

The IEEE Workshop on Test and Validation of High Speed Analog Circuits is designed to address a big aspect of this race: cost and quality. Increasing speed has given rise to a spike in complexity of analog circuits. This has been further stressed by the need for integrating with digital functionality in SOCs. Whether embedding in monolithic dice or integrating in a SiP, integration has thrown its share of problems. Defect coverage alone is no longer sufficient to qualify a die. We need parametric coverage, as early in the manufacturing flow, as possible. This workshop addresses defect and parametric coverage of all analog circuits involved in making high bandwidth communications a reality. The scope of the workshop includes:

SERDES test and characterization
RF circuits test and characterization
Self-healing, self-calibration and self-adaptation techniques
Built-in test and design-for-test
High speed data converter test and characterization
3D and KGD considerations
High speed PLL test and characterization
Clock jitter and skew measurement
Phase noise measurement
Precision delay-line test and characterization
AC and DC supply noise measurement
Analog fault modeling and fault simulation
Analog test bus design
ATE technology
Board technology
Economics of test and yield optimization

Workshop Registration

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You may register for the workshop through the ITC registration website.

Advance Program

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Thursday -- Friday

September 12, 2013 (Thursday)

4:30 PM - 4:45 PM	Session 1: Welcome Address
	General Chair: Amit Majumdar, Xilinx, USA Vice General Chair: Yervant Zorian, Synopsis, USA Program Chair: Haralampos-G. Stratigopoulos, TIMA Laboratory/CNRS, France

4:45 PM - 5:35 PM	Session 2 - Keynote Address: Mobile Devices and need for High-Speed Analog Design and Test Karim Arabi – VP Research & Development, Qualcomm, USA

5:35 PM - 7:00 PM	Panel: Too high frequency to test - what is the quality impact? Organizer/Moderator: Stephen Sunter – Mentor Graphics, Canada
	Panelists: Jacob A. Abraham – University of Texas at Austin, USA John Carulli – Texas Instruments, USA Wei Gao – Broadcom, USA Yiorgos Makris – University of Texas at Dallas, USA

7:30 PM - 9:30 PM WORKSHOP RECEPTION

September 13, 2013 (Friday)

7:00 AM - 8:00 AM WORKSHOP BREAKFAST

8:00 AM - 10:00 AM	Session 4 - Presentations Session Moderator: Jacob Abraham � University of Texas at Austin, USA
8:00 - 8:30	An Effective Hierarchical Test Solution for Interface IP blocks within Complex SoC Gurgen Harutyunyan, Arun Kumar, Avetik Yessayan, Yervant Zorian Synopsys Corp., USA
8:30 - 9:00	The Expanding Role of FPGAs in Low-Cost Multi-GHz Test Systems D. C. Keezer, A. Chatterjee, T. H. Chen, H. W. Choi, S. Y. Kim#, T. Moon, D. Stonecypher, H. Yoo# *Georgia Tech, USA #Samsung Electronics Corp., Korea
9:00 - 9:30	Self-Healing of Analog/RF Circuits: A Statistical Approach X. Li, F. Wang, S. Sun, S. Yaldiz, L. Pileggi, A. Natarajan#,&, M. Ferriss#, J.-O. Plouchart#, B. Sadhu#, B. Parker#, A. Valdes-Garcia#, M. Sanduleanu#, J. Tierno#, D. Friedman# Carnegie Mellon University, USA #IBM T. J. Watson Research Center, USA &Oregon State University, USA
9:30 - 10:00	Process and Environment-Adaptive Wireless Communications Systems A. Chatterjee Georgia Tech, USA

10:00 AM - 10:30 AM COFFEE BREAK

10:30 AM - 12:00 PM	Session 5 - Presentations Session Moderator: Gordon Roberts � McGill University, Canada
10:30 - 11:00	Linearity Improvement Technique of Multi-bit Sigma-Delta TDC for Timing Measurement Yuta Arakawa, Yusuke Oosawa, Haruo Kobayashi, Osamu Kobayash# Gunma University, Japan #Semiconductor Technology Academic Research Center (STARC), Japan
11:00 - 11:30	DFT Technique to Enhance High Speed Serial IO PHY Performance Connie Y. Miao Intel, USA
11:30 - 12:00	Integrated Test Support Features for Multi-GHz DACs in 28nm CMOS Patrick Quinn, Georgi Radulov#, Arthur van Roermund# Xilinx, Ireland #Eindhoven University of Technology, The Netherlands

12:00 PM - 1:00 PM WORKSHOP LUNCHEON

1:00 PM - 2:00 PM	Session 6: Embedded Tutorial
	The Challenges behind Millimeter-Wave Testing and High-Volume Manufacturing: Managing Risk on the path from 6GHz to 96GHz Manufacturing Test Mustapha Slamani, John Ferrario, IBM, USA

2:00 PM - 2:30 PM COFFEE BREAK

2:30 AM - 4:00 PM	Session 7 - Presentations Session Moderator: Patrick Quinn � Xilinx, Ireland
2:30 - 3:00	Analog Implementation of Ontogenic Neural Networks for RF Built-In Self-Test Dzmitry Maliuk, Yiorgos Makris# Yale University, USA #University of Texas at Dallas
3:00 - 3:30	A Comparative Analysis of Indirect Measurement Selection Strategies for Analog/RF Alternate Testing S. Larguech, F. Azais, S. Bernard, V. Kerzerho, M. Comte, M. Renovell LIRMM (CNRS � University of Montpellier 2), France
3:30 - 4:00	The Future of High Speed Electrical IO Testing: Facing Complex Challenges Salem Abdennadher Intel, USA

4:00 PM WORKSHOP CLOSURE

More Information

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For general information contact:
Amit Majumdar
Tel: +408-879-3097
Fax: +408-626-6499
E-mail: amit.majumdar@xilinx.com

Committees

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General Chair
Amit Majumdar, Xilinx

Vice General Chair
Yervant Zorian, Synopsys

Program Chair
Haralampos-G. Stratigopoulos, TIMA

Finance
Chen-Huan Chiang, Alcatel-Lucent

Local Arrangements
Sandeep Gupta, USC

Program Committee (to include)
Jacob A. Abraham, UT Austin
Elad Alon, UC Berkeley
Florence Azais, LIRMM
Abhijit Chatterjee, Georgia Tech
K. T. Tim Cheng, UCSB
Jerzy Dabrowski, Linkoping Univ.
William R. Eisenstadt, Univ. Florida
Oren Eliezer, Xtendwave
Christophe Erdmann, Xilinx
Yohan Frans, Xilinx
David Keezer, Georgia Tech
Haruo Kobayashi, Gunma Univ.
Hervé Le-Gall, STMicroelectronics
Yiorgos Makris, UT Dallas
Cedric Mayor, Presto Engineering
Suriyaprakash Natarajan, Intel
Sule Ozev, Arizona State Univ.
Gordon Roberts, McGill Univ.
Shreyas Sen, Intel
Saghir Shaikh, Broadcom
Mustafa Slamani, IBM
Stephen Sunter, Mentor Graphics
Ping-Ying Wang, MediaTek
Ender Yilmaz, Freescale
Vladimir Zivkovic, d4t-systems

For more information, visit us on the web at: http://users-tima.imag.fr/rms/stratigopoulos/TVHSAC.html

The 3rd IEEE International Workshop on Test and Validation of High Speed Analog Circuits (TVHSAC 2013) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).